cycle
0
1
2
3
4
5
6
7
8
clk
req64n
ack64n
framen
cben[7:0]
F7
00
ad[63:0]
ADDR
1,0
3,2
5,4
7,6
par
par64
devseln
irdyn
trdyn
stopn
dp_start
dp_done
bar_select[2:0]
wr_cyc
wr_be_rdy
0
wr_be_now[7:0]
00
FF
mem_add[11:0]
mem_data_out[63:0]
000
1,0
008
3,2
010
5,4
018
7,6
Figure 6-21 · 64-Bit Burst Write Cycle
Operating Note
When configured with 64-bit functionality, the core should only be used in 64-bit environments. The core does not
implement the logic to allow a 64-bit core to function correctly when inserted into a 32-bit slot. The inclusion of this
logic would significantly increase the amount of FPGA resources the core requires.
70
v4.0
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